1. Field of the Invention
The present invention relates to manufacturing method for a semiconductor device, in particular, a method for forming a shallow trench isolation.
2. Description of the Prior Art
In semiconductor processes, in order to provide good electrical isolation and to avoid short-circuits between electric devices on a wafer, a localized oxidation isolation (LOCOS) process, or a shallow trench isolation (STI) process is used to insolate and protect the devices. Since the field oxide layer of the LOCOS process consumes a great part of the wafer area, and bird's beak can occur when growing the field oxide, an STI process is typically used in the semiconductor processes when the line width is small. An STI process involves first forming a shallow trench between each device, and then filling the trench with an insulating material to obtain an electrical isolation effect between each device.
The conventional manufacturing method to form a shallow trench isolation is shown in FIG. 1. First, a pad oxide layer 12 is formed on the surface of a substrate 10, a silicon nitride (SiN) layer 14 is then formed on the pad oxide layer 12, wherein the SiN layer 14 is used as a hard mask layer, and a patterned photoresist layer (not shown) is formed on the SiN layer 14. Afterwards, an etching process is then carried out to form a trench 20 in the substrate that is not covered by the patterned photoresist layer. The patterned photoresist layer is then removed, and a deposition process, such as a chemical vapor deposition (CVD), is performed to form a filler 24 in the trench 20 which covers the SiN layer 14 and wherein the filler includes silicon oxide (SiO2), a planarization process such as chemical mechanical polishing (CMP) is then carried out to complete a shallow trench isolation (STI).
However, during the planarization process, the grinded level can not be lower than the top of the SiN layer 14, therefore, the height of the STI from the surface of the substrate is limited by the height of the SiN layer 14. Besides, when the planarization process is performed on a large area STI, the etching rate of the STI in the central region is faster than in the periphery region, hence a dishing phenomenon will occur, thereby influencing the quality of the STI.